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1 features ? one-time programmable (otp) feature low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 3.6v) internally organized 16,384 x 8 2-wire serial interface schmitt trigger, filtered inputs for noise suppression bidirectional data transfer protocol 1 mhz (5v), 400 khz (2.7v) and 100 khz (1.8v) compatibility write protect pin for hardware and software data protection 64-byte page write mode (partial page writes allowed) self-timed write cycle (5 ms typical) high reliability ? endurance: 100,000 write cycles ? data retention: 40 years automotive grade and extended temperature devices available 8-lead jedec pdip, 8-lead jedec soic and 8-lead eiaj soic packages description the AT24CS128 provides 131,072 bits of serial electrically-erasable and programma- ble read only memory (eeprom) organized as 16,384 words of 8 bits each. the device?s cascadable feature allows up to 4 devices to share a common 2-wire bus. the device also features a one-time programmable 2048-bit array, which once enabled, becomes read-only and cannot be overwritten. if not enabled, the otp section will function as part of the normal memory array. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the device is available in space-saving 8-lead jedec pdip, 8-lead jedec soic and 8-lead eiaj soic packages. in addition, the entire family is avail- able in 2.7v (2.7v to 5.5v) and 1.8v (1.8v to 3.6v) versions. rev. 1152f?seepr?7/03 2-wire serial eeproms with permanent software write protect 128k (16,384 x 8) AT24CS128 pin configurations pin name function a0 - a2 address inputs sda serial data scl serial clock input wp write protect pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda pin soic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda
2 AT24CS128 1152f?seepr?7/03 block diagram pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/page addresses (a2, a1, a0): the a1 and a0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with at24c32. when the pins are hardwired, as many as four 128k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). when the pins are not hardwired, the default a 1 and a 0 are zero. the a2 device address input is a ?don?t care? input. write protect (wp): the write protect input, when tied to gnd, allows normal write oper- ations. when wp is tied high to v cc , all write operations to the memory are inhibited. if left absolute maximum ratings* operating temperature .................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma a 2
3 AT24CS128 1152f?seepr?7/03 unconnected, wp is internally pulled down to gnd. switching wp to v cc prior to a write operation creates a software write protect function. memory organization AT24CS128, 128k serial eeprom: the 128k is internally organized as 256 pages of 64-bytes each. random word addressing requires a 14-bit data word address. note: this parameter is characterized and is not 100% tested. note: v il min and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +1.8v. symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , scl) 6 pf v in = 0v dc characteristics applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +1.8v to +5.5v, t ac = 0 c to +70 c, v cc = +1.8v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max units v cc1 supply voltage 1.8 3.6 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v read at 400 khz 1.0 2.0 ma i cc2 supply current v cc = 5.0v write at 400 khz 2.0 3.0 ma i sb1 standby current (1.8v option) v cc = 1.8v v in = v cc or v ss 1.0 a v cc = 3.6v 3.0 i sb2 standby current (2.7v option) v cc = 2.7v v in = v cc or v ss 2.0 a v cc = 5.5v 5.0 i sb3 standby current (5.0v option) v cc = 4.5 - 5.5v v in = v cc or v ss 5.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (note:) -0.6 v cc x 0.3 v v ih input high level (note:) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc3 = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
4 AT24CS128 1152f?seepr?7/03 notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.7v, 5v), 10 k ? (1.8v) input pulse voltages: 0.3v cc to 0.7v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5v cc ac characteristics applicable over recommended operating range from t a = -40 c to +85 c, v cc = +1.8v to +5.5v, cl = 100 pf (unless oth- erwise noted). test conditions are listed in note 2. symbol parameter 1.8-volt 2.7-volt 5.0-volt units min max min max min max f scl clock frequency, scl 100 400 1000 khz t low clock pulse width low 4.7 1.3 0.4 s t high clock pulse width high 4.0 0.6 0.4 s t aa clock low to data out valid 0.1 4.5 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 4.7 1.3 0.5 s t hd.sta start hold time 4.0 0.6 0.25 s t su.sta start set-up time 4.7 0.6 0.25 s t hd.dat data in hold time 0 0 0 s t su.dat data in set-up time 200 100 100 ns t r inputs rise time (1) 1.0 0.3 0.3 s t f inputs fall time (1) 300 300 100 ns t su.sto stop set-up time 4.7 0.6 0.25 s t dh data out hold time 100 50 50 ns t wr write cycle time 20 10 10 ms endurance (1) 5.0v, 25c, page mode 100k 100k 100k write cycles
5 AT24CS128 1152f?seepr?7/03 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (refer to data validity timing diagram). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (refer to start and stop definition timing diagram). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowl- edge that it has received each word. standby mode: the AT24CS128 features a low-power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high.
6 AT24CS128 1152f?seepr?7/03 bus timing (scl: serial clock, sda: serial data i/o) write cycle timing (scl: serial clock, sda: serial data i/o) note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. data validity t wr (1) stop condition start condition wordn ack 8th bit scl sda
7 AT24CS128 1152f?seepr?7/03 start and stop definition output acknowledge
8 AT24CS128 1152f?seepr?7/03 device addressing the 128k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to figure 1). the device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. this is common to all 2-wire eeprom devices. the 128k uses the two device address bits a1, a0 to allow as many as four devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will retu rn to a standby state. data security: the AT24CS128 has a hardware data protection scheme that allows the user to write protect the whole memory when the wp pin is at v cc . write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receip t of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero. the addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (refer to figure 2). page write: the 128k eeprom is capable of 64-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must ter- minate the page write sequence with a stop condition (refer to figure 3). the data word address lower 6 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero, allowing the read or write sequence to continue.
9 AT24CS128 1152f?seepr?7/03 otp description/ operation the otp feature provides the user with a 2048-bit (256 x 8) security section, which once programmed and enabled, becomes read-only and data cannot be changed or overwrit- ten. the otp section is located in the upper 2k section of the memory array in the AT24CS128. if not enabled, the otp section will function as part of the normal memory array. to enable the otp section: 1. inputs must be connected: a2 = don?t care, a1 and a0 = v cc or gnd 2. initiate the programming sequence: start 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx stop once enabled, previously written data cannot be changed. the status of the otp sec- tion can only be confirmed by initiating a programming sequence to the otp section and verifying by a read command. the use of the write protect (wp) feature can be utilized with or without enabling the otp function. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition (refer to figure 4). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 5). sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequen- tial read will conti nue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condi- tion (refer to figure 6).
10 AT24CS128 1152f?seepr?7/03 figure 1. device address figure 2. byte write figure 3. page write (* = don?t care bit) (? = don?t care bit for the 128k)
11 AT24CS128 1152f?seepr?7/03 figure 4. current address read figure 5. random read (* = don?t care bit) (? = don?t care bit for the 128k) figure 6. sequential read
12 AT24CS128 1152f?seepr?7/03 note: for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics table s. AT24CS128 ordering information ordering code package operation range AT24CS128-10pi-2.7 AT24CS128n-10si-2.7 AT24CS128w-10si-2.7 8p3 8s1 8s2 industrial (-40 c to 85 c) AT24CS128-10pi-1.8 AT24CS128n-10si-1.8 AT24CS128w-10si-1.8 8p3 8s1 8s2 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline (eiaj soic) options -2.7 low-voltage (2.7v to 5.5v) -1.8 low-voltage (1.8v to 3.6v)
13 AT24CS128 1152f?seepr?7/03 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
14 AT24CS128 1152f?seepr?7/03 8s1 ? jedec soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. note: 10/10/01 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 a h 1 2 n 3 top view c e end view a b l a2 e d side view common dimensions (unit of measure = mm) symbol min nom max note this drawing is for general information only. refer to jedec drawing ms-012 for proper dimensions, tolerances, datums, etc. a ? ? 1.75 b ? ? 0.51 c ? ? 0.25 d ? ? 5.00 e ? ? 4.00 e 1.27 bsc h ? ? 6.20 l ? ? 1.27
15 AT24CS128 1152f?seepr?7/03 8s2 ? eiaj 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 5/2/02 8s2 b top view side view end view h 1 n c e a b l a1 e d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm . a 1.78 2.03 a1 0.05 0.33 b 0.35 0.51 5 c 0.18 0.25 5 d 5.13 5.38 e 5.13 5.41 2, 3 h 7.62 8.38 l 0.51 0.89 e 1.27 bsc 4
printed on recycled paper. 1152f?seepr?7/03 xm disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof, are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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